Currently, hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft. The rapidly growing gap between silicon capacity and design productivity has resulted in a pressing need for design reuse. Hardware building blocks, usually under the name of cores, have become increasingly popular as an efficient way of reusing design intellectual property (IP). While several potential classification schemes exist for integrated circuits (IC) IP, the classification of cores according to levels of implementation details is popular. Hard cores are IPs completely implemented using a particular physical design library. Firm cores are also completely implemented, including physical design, but are targeted at a symbolic library. Finally, soft cores are described in high level languages such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog.
While hard cores provide complete information about all relevant design parameters and facilitate high levels of performance and implementation parameter optimization for the selected library, soft cores are superior in terms of flexibility and application range. Initially, hard cores dominated the IP reuse market and practice, but recently there is an increasing trend toward other types of cores and in particular, soft cores. Additionally, parameterized, configurable, and programmable cores have been rapidly gaining popularity.
Although IC component reuse has been widely practiced at many design centers since the beginnings of silicon designs, in the last few years a strong consensus has formed that IP reuse will be a dominant enabling force for the future generation of designs. A number of design companies have been making strong efforts to develop their IP portfolio, often mainly for internal use. There are also several companies who have completely based a business model on providing design IP. Thus, IP creation, assembly, and testing have received significant recent research attention.
The Viterbi decoding process has by far been the most widely studied and used convolutional error correction code in both wired and wireless communication. Viterbi decoding is considered a fundamental Digital Signal Processing (DSP) method and the performances of modern DSP chips are often quoted in terms of a Viterbi decoding speed.
Filtering (i.e., processing) on streams of data is another fundamental task widely used in digital signal processing, communication, and control applications. Infinite Impulse Response (IIR) filters are particularly attractive due to a relatively low implementation complexity. A variety of different topological structures have been proposed for the realization of IIR filters, including direct form, cascade, parallel, continued fraction, ladder, wave digital, state-space digital, orthogonal and multi-variable digital lattice. Today, in addition to many public domain IIR filter design programs, there are also well supported commercial design tools for synthesis of IIR filters.
Technique selection and design has been a popular research topic in a number of research fields, particularly in artificial intelligence where four main directions have emerged: first order logic-based methods, rewrite systems, transformational approaches and schematic-based programming. While the four techniques are strategically and procedurally very different, the techniques all share a common weakness in an inability to scale to problems of practical importance. Several very large scale integration DSP efforts have also addressed the method selection and design process.
Multi-resolution techniques have been popular for a long time, in particular in image, video, and in general, digital signal processing. The popularity of multi-resolution techniques in DSP has been further amplified with the introduction of wavelet transforms. Multi-resolution techniques have also been widely used in numerical techniques and in mesh-based finite element techniques.
In most modern communication systems, channel coding is used to increase throughput, add error detection and correction capabilities, and provide a systematic way to translate logical bits of information to analog channel symbols used in transmission. Convolutional coding and block coding are the two major forms of channel coding used today. In convolutional coding, the output is based on a current input and a current state with no defined end while in block coding chunks of input data are processed at a time. Generally, convolutional coding is better suited for processing continuous data streams with relatively small latencies. Also, since convolutional forward error correction (FEC) works well with data streams affected by the atmospheric and environmental noise (i.e., Additive White Gaussian Noise) encountered in satellite and cable communications, convolutional coders have found widespread use in many advanced communication systems.
Convolutional codes are usually defined using the two parameters, code rate (k/n) and constraint length (K). The code rate of the convolutional encoder is calculated as the ratio k/n where k is the number of input data bits and n is the number of channel symbols output by the encoder. The constraint length K is directly related to the number of registers in the encoder. The (shift) registers hold the previous data values that are systematically convolved with the incoming data bits. The redundancy of information in the final transmission stream is a key factor enabling the error correction capabilities used when dealing with transmission errors.
Referring to FIG. 1, an example of a conventional rate convolutional encoder 20 with K=3 (i.e., four states) is shown. The conventional encoder 20 generates two channel symbols (i.e., S1 and S2) as each incoming data bit is shifted into register flip-flops R1 and then R2. Connections from the registers R1 and R2 to the output XOR gates X1 and X2 are defined by a polynomial G. There are many studies that show the optimal K and G in different situations. Although the rate encoding effectively reduces the raw data throughput by a factor of two, the power savings gained due to the increased reliability of the channel offset the negative effects of the reduced throughput and overall, the technique improves the efficiency of the channel.
Viterbi decoding and sequential decoding are currently the two main types of processes used with convolutional codes. Although sequential decoding performs very well with long-constraint-based convolutional codes, sequential decoding has a variable decoding time and is less suited for hardware implementations. On the other hand, the Viterbi decoding process has fixed decoding times and is well suited for hardware implementations. An exponentially increasing computation criteria as a function of the constraint length K limits current implementations of the Viterbi decoder to about a constraint length K equal to nine.
Viterbi decoding, also known as maximum-likelihood decoding, comprises the two main tasks of updating a trellis and trace-back. The trellis used in Viterbi decoding is essentially the convolutional encoder state transition diagram with an extra time dimension. The trace-back is used to determine the most likely bit sequence received by the encoder 20.
Referring to FIG. 2, an example of a conventional trellis diagram 22 for a four-state (i.e., K=3) Viterbi decoder is shown. The four possible convolutional encoder states are depicted as four rows (i.e., 00, 01, 10 and 11) in the trellis diagram 22. Solid arrows represent branch transitions based on logical “1” inputs to the encoder 20 and the dashed arrows represent branch transitions based on logical “0” inputs to the encoder 20. The encoder 20 produces two channel symbols S1 and S2 associated with each branch in the trellis 22.
After each time instance or step t, elements in the column t contain the accumulated error metric for each encoder state, up to and including time t. Every time a pair of channel symbols S1 and S2 is received, the process updates the trellis by computing a branch metric associated with each possible transition. In hard decision decoding, the branch metric is most often defined to be the Hamming distance between the channel symbols S1 and S2 and the symbols 00, 01, 10 and 11 associated with each branch. For the hard decision rate decoding at two channel symbols per branch, the possible branch metric values are 0, 1, and 2, depending on the number of mismatched bits. The total error associated with taking each branch is a sum of the branch metric and the accumulated error value of a state metric from which the branch initiates. Since there are two possible branch transitions into each state, the smaller of the two accumulated error metrics is used to replace the current state metric value of each state.
The state with the lowest accumulated error metric is determined as the candidate for trace-back. A path created by taking each branch leading to the candidate state is traced back for a predefined number of steps. An initial branch in the trace-back path indicates the most likely transition in the convolutional encoder 20 and is therefore used to obtain the actual encoded bit value in the original data stream.
To make the decoder work, received channel symbols S1 and S2 are quantized. In hard decision decoding, channel symbols S1 and S2 are each either a logical “0” or a logical “1”. Hard decision Viterbi decoders are extremely fast due to the small number of bits involved in the calculations. However, tremendous bit error rates (BER) improvements have been achieved by increasing the number of bits (resolution) used in quantizing the channel symbols S1 and S2.
Referring to FIG. 3, an example of a conventional uniform quantizer function 24 using 3-bits (eight levels) to represent a symbol received on the channel is shown. An energy per symbol to noise density ratio (i.e., Es/No) is used to calculate a decision level (i.e., D). The decision level D is then used to determine the branch metrics to a higher precision than just 0, 1 or 2. The higher precision branch metrics in turn create higher precision state metrics. The benefits of soft decision over hard decision decoding are offset by the cost of significantly bigger and slower hardware.